1. Field of the Invention
The present invention relates to a semiconductor device package, and more particularly, to a semiconductor device package in which a plurality of semiconductor chips are stacked.
2. Description of the Related Art
To realize high-density arrangement of semiconductor chips, a key technology for reducing electronic device dimensions and weight, a variety of semiconductor packaging techniques have developed.
Semiconductor packaging structures requiring reduced area for installation, e.g., onto a motherboard, include: a pin-insert package such as DIP (Dual Inline Package); a surface installation package, such as SOP (Small Outline Package), performed by leading a periphery; and a package such as BGA (Ball Grid Array) in which external output terminals are disposed on an under surface of the package in a lattice manner. Further, techniques for realizing high-density installation by reducing an area ratio of a package with respect to semiconductor chips include various efforts to narrow a pitch of the external output terminals and reduce a package size by making finer substrate wiring.
Further, a multi-chip package, e.g., a plurality of semiconductor chips installed as a single package, has been developed as a chip-stacked package, e.g., a plurality of semiconductor chips stacked, to realize a higher-density installation. The multi-chip package may include a system-in package in which a plurality of semiconductor chips having different functions are sealed and interconnected for operation as a coordinated multi-chip system within a single package.
Meanwhile, in the context of making an electronic device smaller, lighter, and thinner, another method is gaining attention. This method uses a “system-on chip” approach wherein circuits such as a memory circuit, a logic circuit, and an analog circuit conventionally provided separately are provided in combination and integrated in a single semiconductor chip operating as a single-chip system.
However, incorporating circuits such as the memory circuit and the logic circuit into a single chip raises several problems. It is difficult to reduce a voltage of the memory circuit and it is necessary to perform an additional process for reducing noises occurring in the logic circuit. Further, when an analog circuit, which has been conventionally constituted of a bipolar member, is provided in combination with other circuits it is difficult to manufacture the analog circuit by using the same CMOS as the memory circuit and the logic circuit.
Under such circumstances, the “system-in package” (SIP) approach has received more attention than the “system-on chip” approach, the SIP being better adapted for a shorter development period and at lower cost.
A conventional semiconductor chip design, however, usually determines the positions of, for example, a chip pad and the like without considering the semiconductor chip a component in a SIP. Thus, when forming the SIP each of the semiconductor chips is electrically connected to a printed circuit board (PCB) or substrate using bonding wires, but bonding wires tend to contact each other and can undesirably short. Further, a circuit for a PCB in a SIP can be very complicated, making trace routing difficult when all signals are taken from all semiconductor chip directly.
In addition, a SIP structure may include a plurality of semiconductor chips stacked with the larger chips at the bottom and smaller at the top, e.g., stacked with the chip progressively smaller from bottom to top. This arrangement prevents the one of the stacked semiconductor chips from covering the bonding pads of a lower semiconductor chip. The bonding terminals on the substrate are disposed outside the lowermost semiconductor chip. Thus, when the uppermost semiconductor chip and the lowermost semiconductor chip are different in size, a distance between the bonding pad of the uppermost semiconductor chip and the bonding terminal on the substrate is relatively long, and a corresponding relatively long length of bonding wire is required. Frequently, the logic/analog LSI is much smaller than the memory LSI, i.e., smaller in chip size. Thus, in a semiconductor device arranged with the relatively smaller logic/analog LSI stacked upon the relatively larger memory LSI and with each LSI wire bonded to the other, the wire is necessarily longer. The wire becomes brittle and tends to drop off when the semiconductor chips are sealed. Further, the relatively longer wire has a greater tendency to hang or sag downward due to its relatively greater weight.
In a typical SIP, a memory semiconductor chip and a logic/analog semiconductor chip are stacked on a substrate with the relatively larger memory chip in a lower stack position. However, the number of pins of the upper logic/analog semiconductor chip is large, more than that of the lower memory chip, bonding wires from the memory semiconductor chip and the logic/analog semiconductor chip may be entangled. In other words, the many bonding wires from the upper logic/analog chip must reach over those of the lower memory chip and thereby provide multiple opportunities for undesirable contact, e.g., shorting, therebetween.
Also, to attain a lighter, thinner, smaller SIP and to maintain a high-quality SIP, there exists a need for performing a direct access test on each semiconductor chip of the SIP after formation as a package.